--===========================================================================--
-- Naziv		: Operand fetch
-- Ime fajla	: o_fetch.vhdl  
-- Verzija		: 0.1
--===========================================================================-- 

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity o_fetch is 
	  port (
		   --IN
			reset,clk : in std_logic;
			flush,stall : in std_logic;         
			PC_id    : in std_logic_vector (15 downto 0 ); --PC iz fetch faze; PC se mora prosledjivati
			R1_id,R2_id,R3_id     : in std_logic_vector (3 downto 0 );
			Imm_id         : in std_logic_vector (7 downto 0 );
			opcode_id      : in std_logic_vector(4 downto 0);
			
		   --OUT
			PC_of              : out std_logic_vector (15 downto 0 );
			R1_of,R2_of,R3_of     : out std_logic_vector(3 downto 0);
			Imm_of             : out std_logic_vector (7 downto 0 );
			opcode_of          :out std_logic_vector(4 downto 0)
	  );
end;

architecture o_fetch_AR of o_fetch is
begin
	  o_fetch_PR: process (clk,reset,flush) is
	  begin
		if (reset='1' or flush='1') then
			PC_of<="0000000000000000";
			R1_of<="0000";
			R2_of<="0000";
			R3_of<="0000";
			Imm_of<="00000000";
			opcode_of<="00000";
		elsif rising_edge(clk)  then
			if stall='0' then
				PC_of<=PC_id;
				R1_of<=R1_id;
				R2_of<=R2_id;
				R3_of<=R3_id;
	            opcode_of<=opcode_id;
	            --Ako je instrukcija ROR, ovde se "sredjuje" pomeraj
	            if opcode_id="00010" then
					Imm_of<="0000"&Imm_id(3 downto 0);
				else
				    Imm_of<=Imm_id;
				end if;
			end if;
		end if;
	  end process; 
end o_fetch_AR;